HW-V5-ML550-UNI-G【PDF 28/88 页】EVALUATION PLATFORM VIRTEX-5

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Chapter 3: Hardware Description

A high-level block diagram of the USB interface is shown in Figure 3-6 . The USB B-to-A

cable included in the kit mates with the J22 connector.

R

U2

U20

U9

USB_D-

5

28 USB_DTR_I_B

7

14 USB_DTR_B

C33

USB_VBUS 8

27 USB_DSR_I_B

26 USB_TX_O

3

8

18 USB_DSR_B

13 USB_TX

D34

B33

2 1

3 4

25 USB_RX_I

24 USB_RTS_O_B

4

9

17 USB_RX

12 USB_RTS_B

C34

A33

Virtex-5

FPGA

GND

3

23 USB_CTS_I_B

5

16 USB_CTS_B

D32

USB_D+

4

9

USB_RESET_I_B

1

20 USB_RESET_B

B32

CP2102

12 USB_SUSPEND_O 6

MAX3008

15 USB_SUSPEND C32

UG202_3_06_050806

Figure 3-6:

USB Interface Block Diagram

LVDS Connectors

The ML550 Development Board provides 53 pairs of transmit signals and 53 pairs of

receive LVDS signals. These signals are distributed across three Samtec QSE-DP connectors

for transmitting and another three connectors for receiving. Appendix A, “LVDS,” lists the

pinouts.

Transmit LVDS

The LVDS transmit connectors are shown on schematic pages 6 (TX1, P73, U9 bank 17),

7 (TX2, P46, U9 bank 21) and 8 (TX3, P49, U9 bank 22).

ML550 schematic 0381218 sheet 7 shows FPGA U9.AJ26/AJ25 FPGA_CLKP/N from the

FPGA driving a clock multiplier device U16 detailed on sheet 12. On sheet 12, the U16

ICS8745B clock multiplier is configured in clock-doubler mode. U16 receives the

FPGA_CLKP/N clock waveform on it’s input pins U16.1 and U16.2, and outputs a

doubled frequency on pins U16.13 and U16.12, XMITCLK_P and XMITCLK_N

respectively. This doubled output clock is wired to a Samtec LVDS transmit connector P46,

pins P46.40 and P46.38, on sheet 7.

Receive LVDS

The LVDS receive connectors are shown on schematic pages 9 (RX1, P74, U9 bank 15), 10

(RX2, P6, U9 bank 19) and 11 (RX3, P3, U9 bank 20).

Each FPGA U9 bank V CCO is 2.5V, and the intended signalling standard for the LVDS

interface is LVDS_25.

ML550 schematic 0381218 sheet 10 shows FPGA U9.E28/F28 DIVCLKP/N driven from a

clock divider device U17 detailed on sheet 12. On sheet 12, the U17 On Semi NB6N239S

clock divider is configured in divide-by-2 mode. U17 receives the clock waveform from the

Samtec LVDS receive connector P6 pins P6.47 and P6.49, on sheet 10. This RCVCLK_P and

RCVCLK_N clock waveform drives U17 input pins U17.2 and U17.3 respectively. U17 then

28

ML550 Networking Interfaces Platform

UG202 (v1.4) April 18, 2008

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